Dynamic Random Access Memory (DRAM) devices continue to be a preferred memory for storing data in electronic systems. DRAMs, due to their small memory cell size, can store large amounts of data in very small devices. At the same time, with the advent of low power electronic devices, such as portable computers and the like, the need to reduce power consumption continues to be an important goal for designers of DRAMs.
Refresh operations, however, must be accomplished while addressing two competing interests. First, the refresh operation must restore data values. Frequent refresh operations are desirable to ensure that data are not corrupted. At the same time, the amount of current required to charge the memory cells results in increased power consumption. Therefore, frequent refresh operations are not desirable as they consume power. These competing interests result in each memory cell being refreshed before a maximum theoretical “pause” time passes.
In a typical DRAM array, the memory cells of the same row are accessed by activating a word line common to the row. Because of this, the memory cells are refreshed on a row-by-row basis. To ensure that each row is refreshed, the DRAM typically includes a “refresh” counter. The refresh counter is set to an initial row address, resulting in the initial row being refreshed. Under control of a refresh clock, the refresh counter is then changed (typically by an increment or decrement operation) to a next row address. This results in the next row address being refreshed. Once a last row address has been reached, the refresh counter returns to the initial row address. In this manner, under control of the refresh clock, the refresh counter cycles through all of the rows in the memory device. The speed of the refresh counter, therefore, determines the rate at which memory cells are refreshed. In order to meet the maximum pause time, the refresh counter must typically cycle through all of the row addresses within the maximum pause time. The refresh clock controls the speed of the refresh counter. If the maximum pause time (the maximum time for which stored data do not corrupt) is T and there are X rows, then the counter period is T/X.
A DRAM device can be expected to operate over a range of temperatures. This gives rise to a problem associated with prior art refresh circuits. While the maximum pause time may be a certain value at one temperature, it can be a different value at another temperature. The pause time of a DRAM cell has been found to roughly double for every 12–15° C. drop in temperature. Thus, as the operating temperature drops, the memory cells do not need to be refreshed as frequently. Therefore, if refresh rates can be adjusted for temperature, DRAM power consumption may be lessened, which is especially desirable for battery powered devices.
U.S. Pat. No. 6,560,164, U.S. Pat. No. 6,281,760 and U.S. Pat. No. 5,278,796, the entirety of which are hereby incorporated by reference herein, describe circuits that adjust the DRAM refresh rate based on the ambient temperature in order to reduce the power consumed by refreshing the memory cells. The temperature sensors of these prior art circuits detect temperature constantly, rendering the temperature sensor always “on” or “active” and thus constantly consuming power.
Therefore, there remains a need for an improved less power consumption temperature-dependent refresh circuit and temperature-dependent method of refreshing memory cells.